Ferroelectric memory devices, like other semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically include one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage.
The ferroelectric memory cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry. Such devices are typically organized internally into blocks, sections, segments, rows and columns. For example, a 6M device may include 2 blocks of 3M each, the blocks each consisting of 6 sections which contain 16 segments, Each segment contains 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each of the 64 columns is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
Data in a ferroelectric data cell is read by connecting the cell capacitor on a first bitline and a reference voltage on a complementary bitline to the input terminals of a differential sense amp. The plateline of the accessed cell is then pulsed. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1” (V“1”). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is amplified and applied to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local IO lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device.
In a typical ferroelectric memory read sequence, two sense amp terminals or bitlines are initially equalized to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp terminals via the bitline to which the cell is connected. Thereafter, a reference voltage is connected to the remaining sense amp terminal, and the sense amp senses the differential voltage across the terminals and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”. The sense amp terminals are then coupled to complimentary local IO lines, which were previously precharged to a predetermined voltage state, such as VDD. The sense amp drives one of the local IO lines to a different voltage state, by which the read data state is passed to an IO buffer circuit. In a write operation, the sense amp and bitline terminals are connected to the local IO lines, which are driven to opposite voltage states depending on the data to be written. One bitline connects to the ferroelectric memory cell for storage of the data written into the ferroelectric capacitor.
FIGS. 1A and 1B illustrate a ferroelectric memory device 2 organized in a folded bitline architecture, wherein a segment portion of the device 2 has 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN, where each column of cells is accessed via a pair of complimentary data bitlines BLCOLUMN and BLCOLUMN′. One column of the device 2 is illustrated in FIG. 1B, in which cells C1-1 through C1-64 form a data word accessible via a wordline WL1 and complimentary bitline pairs BL1/BL1′ through BL64/BL64′. The cell data is sensed during data read operations using sense amp circuits 12 (S/A C1 through S/A C64) associated with columns 1 through 64, respectively. In a typical folded bitline architecture ferroelectric memory device, the cells CROW-COLUMN individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bitlines associated with the cell column and a plateline, where the other bitline is selectively connected to a reference voltage.
In the device 2, the sense amps 12 associated with even numbered columns are located at the bottom of the segment, whereas sense amps 12 associated with odd numbered columns are located at the top of the segment. Shared reference generators 8′ and 8 are provided at the top and bottom of the segment columns, respectively. An even column reference generator 8 is provided at the bottom of the segment columns for providing a reference voltage for even numbered columns and an odd column reference generator 8′ is provided at the top of the columns for the odd numbered columns. The reference voltages from the generators 8, 8′ are coupled to one of the bitlines in the columns using one of a pair of switches 8a, 8b, depending upon whether an even or odd numbered wordline is selected. In reading the first data word of the illustrated segment along the wordline WL1 in the device 2, the cells C1-1 through C1-64 are connected to the sense bitlines BL1, BL2 . . . , BL63, and BL64 while the complimentary reference bitlines BL1′, BL2′ . . . , BL63′, and BL64′ are floating. The reference bitlines BL1′, BL2′, . . . , BL63′, and BL64′ are thereafter connected to the reference voltage generators 8, 8′.
As illustrated in FIG. 1B, the ferroelectric memory cells 4 include capacitors (e.g., CFE1, CFE2, . . . , CFE512) constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor CFE in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
In ferroelectric memories, as well as conventional DRAMs, local IO lines LIO/LIO′ are coupled to the sense amp terminals SABL/SABL′ at appropriate times. To conserve chip area, these local IO lines often run parallel to one another and are separated from one another by only a small space. For example LIO lines associated with columns m and n are typically physically placed in the order such as LIOm, LIOm′, LIOn, and LIOn′. As technology improves and feature sizes become smaller, adjacent local IO lines (LIOm and LIOm′, and LIOm′ and LIOn, and LIOn and LIOn′) get closer together. This close spacing can result in significant amount of capacitance coupling between adjacent IO lines that can lead to a significant degradation of signal noise margins.
For example, in a typical device the local IO lines LIO/LIO′ are pre-charged to VDD and are coupled to the sense amp terminals SABL/SABL′ using n-channel transistors 20a, 20b. If two adjacent memory cells associated with columns m and n store a zero, the two pairs of local IO lines LIOm/LIOm′ and LIOn/LIOn associated therewith will have LIOm and LIOn pulled low because a low voltage is stored in the associated two pairs of sense amp terminals. The line to line capacitive coupling between LIOm and LIOm′, and LIOm′ and LIOn will also pull the LIOm′ low. Calculations show that when the LIO/LIO′ pair discharge, the capacitance coupling could reduce the differential signal on complimentary local IO lines. (In the above example the signal difference between LIOm and LIOm′ will be significantly reduced because the LIOm′ is pulled low due to capacitive coupling from LIOm and LIOn). In addition, the reduced differential signal on LIO pair may slow down the response time when this differential analog signal is converted back to a digital signal.
In order to reduce coupling between the local IO lines during a read, shield lines could be inserted between local IO pairs and or adjacent pairs. However, due to limited space between the local IO lines, insertion of such lines may be difficult. In addition, if shielded local IO lines were added, such lines would increase total line capacitance and thereby undesirably increase memory access times.
Therefore, there is a need for improved methods and systems for transferring data between sense amps and local IO lines, and further transferring data between local IO lines and global IO lines.